The present invention relates to a memory device which stores data in a storage unit such as a register, other than a memory cell core, in a standby mode.
Some memory devices are configured to reduce power consumption they are not in use.
FIG. 1 is a diagram of a conventional memory device 300. The memory device 300 includes a core unit 301 and a peripheral unit 302. The core unit includes memory cells. The peripheral unit 302 performs input and output with an external device (not shown). The core unit 301 is controlled to perform only the holding operation (for example, self refresh operation for a DRAM) of storage information when entering a standby state (power saving state). In the standby state, power is not supplied to the peripheral unit 302 other than a decision unit 303 which issues a return to an active state command. When the decision unit 303 issues the return command, the core unit 301 and the peripheral unit 302 return to the active state.
As shown in FIG. 2, the peripheral unit 302 includes a terminal 310, a peripheral circuit 311 (input/output circuits), and a register 312. The register 312 is a storage device other than the memory cells of the core unit 301. The register 312 stores information when the core unit 301 is in the standby state. The information stored in the register 312, for example, indicates the operation after the core unit 301 has returned to the active state and is typically a special mode register set (SMRS) used in a graphics memory.
However, when the memory is a synchronous memory, such as a synchronous dynamic random access memory (SDRAM), an accurate value cannot be stored in a register because all of the units except the decision unit 303 enter the standby state.
A synchronous memory device latches a signal provided to each input terminal in synchronism with a clock signal ck as shown in FIG. 3 even if it is in the standby state. Therefore, the register 312 of the peripheral unit 302 can latch input data after a period i during which the decision unit 303 determines a command has elapsed in the case where the latch circuit of the decision unit 303 always operates and the latch circuit of the peripheral unit 302 enters the standby state.
However, as shown in FIG. 3, the latch time does not guarantee that valid data is available. Accordingly, the register 312 fails to store the correct data. This problem occurs particularly when the logic process is performed by a plurality of logic stages to determine a command (the period i is long). Therefore, the entire peripheral unit 302 must always be made to enter the active state for the synchronous memory device when the register 312 stores information and the core unit 301 is in the standby state. This increases the power consumption of the peripheral unit 302 regardless of the active/standby state of the core unit 301.